1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with an air gap and a method for fabricating the same.
2. Description of the Related Art
In general, a semiconductor device such as a DRAM (dynamic random access memory) includes a plurality of first conductive structures and a plurality of second conductive structures which are formed between the first conductive structures with a dielectric layer interposed therebetween. For example, the first conductive structures may include gate electrodes, bit lines, metal lines, etc. The second conductive structures may include contact plugs, storage node contact plugs, bit line contact plugs, through vias, and the like.
As a semiconductor device is highly integrated, a gap between the first conductive structure and the second conductive structure gradually decreases. Due to the decreased gap, the parasitic capacitance between the first conductive structure and the second conductive structure increases. In particular, in the case of a DRM in which a bit line and a storage node contact plug adjoin each other, as the parasitic capacitance between the bit line and the storage node contact plug increases, an operation speed slows down and a refresh characteristic is degraded.
In order to reduce the parasitic capacitance, a method of minimizing an area (hereinafter, referred to as a ‘facing area’) where the first conductive structure and the second conductive structure face each other has been suggested. Otherwise, in order to reduce the parasitic capacitance, it is necessary to increase a gap (i.e., distance) between the conductive structures. However, in order to reduce the size of a product to increase an integration degree, there are some limitations in increasing the gap. Also, another effective way of reducing the facing area is to decrease the height of any one of the first conductive structure and the second conductive structure. Nevertheless, if the height is decreased, resistance increases.
Thus, the best way of reducing the parasitic capacitance is to decrease the dielectric constant of the dielectric layer formed between the first conductive structure and the second conductive structure. The dielectric layer generally used in a semiconductor device includes a silicon oxide and a silicon nitride. The silicon oxide has the dielectric constant of about 3.9, and the silicon nitride has the dielectric constant of about 7.
Since the silicon oxide and the silicon nitride have still high dielectric constants, restrictions may exist in reducing the parasitic capacitance.